핸즈프리 통신을 위한 다중 채널 음성 픽업 임베디드 시스템 설계
DC Field | Value | Language |
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dc.contributor.author | 주형준 | - |
dc.date.accessioned | 2017-02-22T07:25:17Z | - |
dc.date.available | 2017-02-22T07:25:17Z | - |
dc.date.issued | 2006 | - |
dc.date.submitted | 56798-05-24 | - |
dc.identifier.uri | http://kmou.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002176385 | ko_KR |
dc.identifier.uri | http://repository.kmou.ac.kr/handle/2014.oak/10786 | - |
dc.description.abstract | Recently, The hands-free communication systems are required for the safety of driving in the environment of inside noisy automobile. Among the most popular hands-free algorithm, array processing algorithm is most widely used. Since the primary advantage of using an array is to enhance a desired signal and reject jamming interferences, array signal processing is essential to satisfy demand of user. In general, array beamforming algorithm is a spatial filtering operation performed on the data received by an array of sensors, such as antennas, hydrophones, or microphones. It provides a system with the ability to “listen” directionally even when the individual microphone in the array are omnidirectional. Therefore, in this thesis, the multi-channel speech pickup system using the array beamforming algorithm for enhancement of calling quality is presented. An FPGA system has better performance than any other system, which is multiprocessing systems with high-performance DSPs. This advantage is due to the simplicity of the core calculation, the limitations of the DSP’s address calculation hardware, and the ability to customize the I/O of the FPGA to the application. For real-time operation, the enhanced speech pickup (beamforming) hardware must calculate all of the beams of interest for each set of new samples | - |
dc.description.abstract | in other words, as implied by the computational requirements discussed earlier, all beams must be calculated at the sensor sample rate. Therefore this thesis implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. A Nios-II processor system is equivalent to a microcontroller or “computer on a chip” that includes a CPU and a combination of peripherals and memory on a single chip. Furthermore, this thesis describe method of designed using on-chip peripherals, and interfaces to off-chip memories and peripherals (SRAM, Flash memory, DMA, et al.). To verify the effectiveness of implemented speech pickup system on Nios-II processor, the results of Niso-II processor are compare with results of computer simulation (MATLAB) and conventional DSP processor (TMS320C6711). According to the results of the speech pickup system on Nios-II processor showed a good agreement with those of computer simulation (MATLAB) and conventional DSP processor (TMS320C6711). | - |
dc.description.tableofcontents | 그림차례 iii 기호표 v 약어표 vi Abstract vii 제1장. 서론 = 1 제2장. 빔 형성기 알고리즘 = 4 제2-1절. 등 간격의 선형 배열에서의 기본 빔 형성 기법 = 4 2-1-1. Delay-and-Sum 빔 형성 기법 = 4 2-1-2. 주파수 영역 빔 형성 기법 = 6 제2-2절. 최적화 빔 형성 기법 = 9 2-2-1. Minimum Mean Square Error 빔 형성기 = 9 2-2-2. Minimum Variance 빔 형성기 = 11 2-2-3. SINR을 최대화 하는 빔 형성기 = 12 제2-3절. 보간 필터를 갖는 빔 형성기 = 14 2-3-1. Zero-Padding 보간법 = 14 2-3-2. 보간 필터를 갖는 Delay-and-Sum 빔 형성기 = 16 제3장. 빔 형성기 하드웨어 설계 기법 = 17 제3-1절. SHARC DSP로 구현한 빔 형성기 = 17 제3-2절. FPGA 멀티 컴퓨터 보드를 이용한 빔 형성기 = 19 제3-3절. Two-level 멀티 컴퓨터를 이용한 빔 형성기 = 22 제3-4절. DSP를 연동한 빔 형성기 = 23 제4장. 보간 필터를 갖는 Delay-and-Sum 빔 형성기의 FPGA 설계 = 25 제4-1절. 빔 형성기를 위한 프로세서 설계 = 26 제4-2절. 시뮬레이션 및 시스템 적용 결과 = 35 4-2-1. Zero-Padding 보간법에 대한 결과 분석 = 35 4-2-2. 설계된 Delay-and-Sum 빔 형성기의 결과 분석 = 42 제5장. 결론 = 47 참고문헌 = 49 | - |
dc.language | kor | - |
dc.publisher | 한국해양대학교 대학원 | - |
dc.title | 핸즈프리 통신을 위한 다중 채널 음성 픽업 임베디드 시스템 설계 | - |
dc.title.alternative | A Design of Multi-channel Speech Pickup Embedded System for Hands-free Communication | - |
dc.type | Thesis | - |
dc.date.awarded | 2006-02 | - |
dc.contributor.alternativeName | Ju | - |
dc.contributor.alternativeName | Hyung-jun | - |
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