1GBps급 유럽형 CATV 하향 스트림 채널 부호화 알고리즘 FPGA 구현

Abstract

Originally, cable networks were established to provide TV signals to a community that otherwise could not receive reliable TV signals. With subsequent addition of more channels, cable TVs have gained enormous popularity in the general segment as well. With the advent of the Internet and other digital communications, however, cable networks and channels have become a focus for transmitting digitized information at high speed and bandwidth. This is because a cable network can provide a high speed digital communication channel in addition to well known traditional cable services.

In cable networks, cable modems provide high speed data transporting functions between a cable network and a connected user. Cable modems typically are implemented by a forward error correction(FEC) scheme. The ITU-T Recommendation J-38 Annex B specifies using 64- and 256- quadrature amplitude modulation (QAM). The cable transmission block includes an FEC encoder, an FEC decoder, and a cable channel. The FEC encoder encodes data using conventional FEC schemes for transmission to the FEC decoder through the cable channel.

One of candidate coding schemes is a concatenate coding scheme which is combined RS code and convolutional code. Concatenate coding schemes are considered as being the best solution for powerful protection of digital information against nonlinear and fading noise channel. However, the convolutional code is not appropriate to high-order modulation such as 64-QAM and 256-QAM. Therefore instead of using convolutional code, TCM(Trellis Coded Modulation) is best solution for cable modem. The FEC encoder includes a Reed Solomon (RS) encoder, a convolutional interleaver, a randomizer (e.g., scrambler), and a Trellis Coded Modulation (TCM) encoder.

This thesis analyzed the performance of cable modem by computer simulation and implemented the cable modem by FPGA chip.

In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and frame-synchronization in decoder, the system recognize that all data is error. This thesis solves the problems by using simple 5-stage registers and unique sync-word.

Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex II pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.