PFC용 부스트 컨버터의 병렬화에 의한 효율 개선
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 전내석 | - |
dc.date.accessioned | 2017-02-22T02:25:40Z | - |
dc.date.available | 2017-02-22T02:25:40Z | - |
dc.date.issued | 2004 | - |
dc.date.submitted | 2006-08-30 | - |
dc.identifier.uri | http://kmou.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002174375 | ko_KR |
dc.identifier.uri | http://repository.kmou.ac.kr/handle/2014.oak/8388 | - |
dc.description.abstract | Switch mode converters have been widely employed to reduce the harmonics of the input current and are increasingly focused on the prevention of accidents and failure in the power system apparatuses. It is desirable that the switching frequency of the switch mode converter be set at a high frequency for effective harmonics reduction. High-frequency operation, however, causes large switching power losses and degradation of the efficiency of the power conversion. This paper proposes a new technique to reduce the switching power loss for single-phase switch-mode boost converter. The rectifier includes an additional converter that parallels the main high-frequency switching device. The additional converter, which is operated at lower frequencies, bypasses almost all the current in the main switch and the high frequency switching loss is greatly reduced. The converter achieves high performances at steady-state and transient conditions as it were the conventional converter driven by one high speed switching. Both switching devices are controlled by a simple method | - |
dc.description.abstract | each controller consists of a one-shot multivibrator, a comparator and an AND gate, and the maximum switching frequency can be limited without any clock generator. The validity of the proposed scheme is verified by computer simulation using software PSIM and experiment, that is the efficiency of the new converter is higher than that of the conventional one by about 8[%]. This paper describes the converter configuration and design, and discusses the steady-state performance concerning the switching loss reduction and efficiency improvement. | - |
dc.description.tableofcontents | 제 1 장 서 론 1 1.1 연구배경 1 1.2 연구내용 5 1.3 논문의 구성 7 제 2 장 역률개선방식 8 2.1 역률개선회로 9 2.2 역률개선회로의 제어 17 2.3 전류 THD 및 역률 23 제 3 장 병렬 컨버터 시스템 31 3.1 회로구성 및 제어방법 31 3.2 동작모드 36 3.2.1 연속 전류모드 동작 36 3.2.2 불연속 전류모드 동작 41 3.3 상태공간 평균화 모델 48 3.3.1 연속 전류모드 동작 48 3.3.2 불연속 전류모드 동작 52 제 4 장 시뮬레이션 및 실험 57 4.1 반도체 스위치의 스위칭 손실 57 4.2 시뮬레이션 62 4.3 실험장치 구성 83 4.4 결과 및 고찰 85 제 5 장 결 론 92 참고문헌 94 | - |
dc.language | kor | - |
dc.publisher | 한국해양대학교 대학원 | - |
dc.title | PFC용 부스트 컨버터의 병렬화에 의한 효율 개선 | - |
dc.title.alternative | Efficiency Improvement of Boost Converter for Power Factor Correction using Parallel-Switch | - |
dc.type | Thesis | - |
dc.date.awarded | 2004-08 | - |
dc.contributor.alternativeName | Jeon | - |
dc.contributor.alternativeName | Nae Seok | - |
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