한국해양대학교

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광대역 무선 통신을 위한 고속 적응형 터보 복호기 FPGA 설계

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dc.contributor.author 최덕군 -
dc.date.accessioned 2017-02-22T05:51:03Z -
dc.date.available 2017-02-22T05:51:03Z -
dc.date.issued 2006 -
dc.date.submitted 56824-08-21 -
dc.identifier.uri http://kmou.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002174627 ko_KR
dc.identifier.uri http://repository.kmou.ac.kr/handle/2014.oak/8689 -
dc.description.abstract This thesis proposes an adaptive turbo decoding algorithm for high order modulation scheme combined with original design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder processes the received symbols recursively to improve the performance. As the number of iterations increases, the execution time and power consumption also increase as well. To reduce the latency and power consumption, this thesis employs the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. This thesis implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, it was found that the decoding speed of proposed adaptive decoding is faster than that of conventional scheme by 6.4 times under the following conditions : N=212, iteration=3, 8-states, 3 iterations, and 8PSK modulation scheme. -
dc.description.tableofcontents Chapter I. Introduction = 1 Chapter II. Adaptive Turbo Decoding Algorithm = 4 2.1 Mapping of bits to signal = 7 2.2 Coset Symbol Transformer(CST) = 8 2.3 Phase Sector Quantizer(PSQ) = 10 2.4 Simulation Results = 13 Chapter III. High Speed Turbo Decoder Algorithm = 15 3.1 Radix-4 Algorithm = 16 3.2 Dual-Path Processing Algorithm = 18 3.3 Parallel Decoding Algorithm = 21 3.4 Early Stop Algorithm = 22 3.5 Simulation Results = 23 Chapter IV. Design of the Adaptive High-Speed Turbo Decoder = 24 4.1 The Adaptive High-Speed Turbo Decoder Structure = 25 4.2 The Optimum Quantized Bits of the Adaptive Turbo Decoder = 28 4.3 FPGA Implementation = 29 Chapter V. Conclusion = 33 References = 35 -
dc.language eng -
dc.publisher 한국해양대학교 대학원 -
dc.title 광대역 무선 통신을 위한 고속 적응형 터보 복호기 FPGA 설계 -
dc.title.alternative An FPGA Design of High-Speed Adaptive Turbo Decoder for Broadband Wireless Communications -
dc.type Thesis -
dc.date.awarded 2006-08 -
dc.contributor.alternativeName Choi -
dc.contributor.alternativeName Duk-Gun -
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전파공학과 > Thesis
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