시스토릭 구조를 갖는 스마트 안테나 알고리즘의 FPGA 구현

Abstract

The performance of digital mobile radio communication systems is affected by channel fading and interference from co-channel users. The problems can be reduced by the use of array antenna at the base station with the appropriate signal processing and combining of the received signal. So it makes the study about smart antenna that tracks the beam according to the position of users, and improves the communication quality. The algorithm for smart antenna are the method based on Directions-of-Arrival(DOA) estimation, algorithm based on training signal, and Constant Modulus(CM) algorithm and so on. But these methods have weak points. First method must be heavy computational loads to detect the DOA and it should be assumed that the number of array antenna is more than that of interference signal. Second method used extra channel for training signal and it is difficult to make training signal when existing co-channel interference. Third method is difficult to choose the desired signal in case of receiving the signals having the constant amplitude more than one. But the drawback of the above mentioned methods has the difficulty demanding for the real time process because of the algorithm's complexity for implementing as hardware.

In this thesis, we design the smart antenna algorithm for real time processing which is based on QR-decomposition-based recursive least squares(QR-RLS) algorithm. The proposed algorithm for real time process consists of the systolic structure using Givens rotations to calculate the inverse matrix which is necessary for many complexities. The number of bits which describes processing data is decided through the integer simulation. The performances of the proposed algorithm are evaluated via computer simulation in Rayleigh fading channel environment. And it is implemented as VHDL(VHSIC Hardware Description Language) to evaluate the real time processing.