반복 부호의 저복잡도 및 고속 복호 알고리즘과 FPGA 구현에 관한 연구

Abstract

Concatenate coding schemes are considered as being the best solution for powerful protection of digital information against nonlinear and fading noise channel. However, the performance of concatenate coding scheme is away from Shannon's limit. In 1993, Berrou and al introduced a new class of error correcting codes for digital transmission : the "turbo code". Turbo codes have been shown to perform near the capacity limit on the additive white Gaussian noise (AWGN) channels. As a powerful coding technique, turbo code offers great promise for improving the reliability of communication over wireless channels. Another interest area of channel coding scheme is LDPC(Low Density Parity Check) code. The high definition television(HDTV) satellite standard , known as the Digital Video Broadcasting (DVB-S2) transmission system employs a LDPC coding technique as a channel coding scheme. Unlike turbo codes, LDPC codes have easily parallelizable decoding algorithm which consists of simple operation such as addition, comparison and look-up table. Moreover the degree of parallelism is “adjustable” which makes it easy to trade-off throughput and complexity. However DVB-S2 system requires large block size and large number of iterations to near Shannon’s limit. The standard recommends that LDPC coded block size has 64800, and number of iteration is about 70 in the case of half coding rate. A large number of iterations for a large block size give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation in order to implement with low power consumption.

This thesis proposes the two kinds of simplified complexity reduced algorithm. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration’s are required at same performance in comparison with conventional decoder algorithm. Secondly, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. In this way, because early detected edges are not computed from following iterations, the computational complexity of further processing is reduced. However the encoder structure is very complicate. Therefore, it highly required channel coding scheme with simple encoder/decoder structure and good error performance in order to apply for wireless multimedia communications such as Ka-band satellite and wide-band mobile communication systems. Recently, there has been intensive focus on turbo product code(TPC) which has low latency and simple structures compare with turbo code. It achieve near-optimum performance at low signal-to-noise ratio. TPCs are two dimensional code constructed from small component codes. Different than original TPC decoder, which performs row and column decoding in a serial fashion, this thesis proposes a parallel decoder structure to reduce the latency. Furthermore, only one delay element is needed in contrast to two delay elements, i.e., decoding time is halved with this structure while maintaining the same performance level. Therefore, this thesis proposes the parallel TPC decoder and analyzes its performance. From the thesis, we describe the low latency and/or computational algorithm of three iterative codes.