한국해양대학교

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병렬 Turbo Product 부호 복호기의 알고리즘 분석 및 VHDL설계

Title
병렬 Turbo Product 부호 복호기의 알고리즘 분석 및 VHDL설계
Alternative Title
VHDL Design and Analysis of Decoder of Parallel Turbo Product Code
Author(s)
이태길
Publication Year
2004
Publisher
한국해양대학교 대학원
URI
http://kmou.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002174971
http://repository.kmou.ac.kr/handle/2014.oak/9113
Abstract
Recently, the trend of wireless communication is changed from the conventional narrow-band voice service to the wide-band multimedia service. In 1993, Berrou et al introduced a new class of error correcting codes for digital transmission : the "turbo code". Therefore, the important problems of high-speed applications of turbo decoder are decoding delay and computational complexity. Therefore, the real difficulty in the field of channel coding is essentially a problem of decoding complexity of powerful codes.

Another interest area of channel coding scheme is LDPC(Low Density Parity Check) code. But the encoder structure is very complicate. Therefore, it highly required channel coding scheme with simple encoder/decoder structure and good error performance in order to apply for wireless multimedia communications such as Ka-band satellite and wide-band mobile communication systems. Recently, there has been intensive focus on TPC(Turbo Product Code) which has low latency and simple structures compare with turbo code and LDPC. It achieve near-optimum performance at low signal-to-noise ratio. TPCs are two dimensional code constructed from small component codes.

Different than original TPC decoder, which performs row and column decoding in a serial fashion, a parallel decoder structure to reduce the latency is proposed in this thesis. Proposed TPC decoder needs only one delay element in contrast to conventional algorithm, which needs two delay elements.

This thesis analyzes the parallel TPC decoder by mathematical theory and compares the performance between parallel algorithm and conventional algorithm by computer simulation. Also this thesis establishes parameters by fixed-point simulation for VHDL implementation. From results of computer simulation and VHDL implementation, this thesis shows that decoding time of parallel algorithm is halved with this structure while maintaining the same performance level.
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